Subject: Historical Firsts? (I/O)
From: [email-masked] (Mark Smotherman)
Newsgroups: comp.arch,alt.folklore.computers

|> |> 1958	X1:	asynchronous I/O with interrupts (*) (design 1956)
|> |> 1965	X8:	asynchronous block I/O with interrupts (design 1960)
|> 
|> Before 1958: IBM 705 had some sort of asynchronous I/O, I think.
|> 
|> 1958 IBM 709:   Data channels,
|>                 complete with (separate from the main CPU) channel program
|>                 and interrupts.
|> 

Please email me regarding machines that are thought to have historical firsts
in terms of I/O.  I tried to do a nearly-exhaustive study a few years ago
and published "A sequencing-based taxonomy of I/O systems and a review of
historical machines," in ACM Computer Architecture News, v. 17, n. 5, Sept.
1989.  My conclusions regarding historical firsts were:

* I/O interrupts in the NBS DYSEAC,

  NBS DYSEAC (1954) - introduced I/O interrupt [38,39].  This machine has
  two program counters; an I/O signal causes the CPU to switch PCs.  A bit
  in each instruction can force a switch back between PCs.  Codd states,
  "in the NBS DYSEAC the very significant step was made of extending
  interruption to input-output operations" [17].

* DMA in the IBM SAGE (AN/FSQ-7),

  IBM SAGE (or AN/FSQ-7, started 1952, operational 1955) - DMA operation [3].
  I/O operations start block transfers of data to/from drum buffers that
  proceed in parallel with further CPU operations.  A controller generates the
  sequential memory addresses for the block and decrements a counter, while
  the CPU has a conditional branch to test completion of the transfer.
  Transfers are interlocked so that the CPU is stalled if a second transfer is
  attempted before the previous one ends.  Jacobs states "the input/output
  (I/O) break, or memory cycle stealing," was introduced in SAGE [37], and
  Serrell, et al., identify "computation in parallel with I/O" as a significant
  new feature of SAGE [48].

* the interrupt vector concept in the Lincoln Labs TX-2,

  Lincoln TX-2 (1957 paper) - "multiple sequence" [30].  This machine contains
  33 program counters; each I/O device has a dedicated PC and operates at a
  fixed priority (i.e., forerunner of interrupt vector).  Each instruction has
  break and dismiss bits: break is used to indicate points at which a higher-
  priority sequence can take over, while dismiss is used to allow lower-
  priority sequences to resume.

* fully symmetric I/O in the Burroughs D-825 multiprocessor,

  Burroughs D-825 (1960) [2,8,28,53].  All interrupts are transmitted to each
  processor; an OS-controlled mask register in each processor determines if
  it will respond to a given interrupt.

In a competition for a first "channel", well, that term means different things
to different people.  I proposed the following:

  Within this range, I draw a distinction between a controller that can
  transfer only one block before requiring CPU intervention and a controller
  that can transfer multiple blocks in a scatter/gather type of operation
  (in which the blocks are identified to the controller by a chain of
  descriptors).  Some designers and authors call a controller with the latter
  capability an I/O channel.  Indeed, Bell and Newell categorize controllers
  with scatter/gather capability as Pios, since they consider the chain of
  block descriptors to be a series of jump instructions [8].  However, in this
  taxonomy I reserve the term I/O channel for a specialized I/O processor that
  fetches instructions with identifiable opcode fields.  Moreover, I also use
  the distinction made by Blaauw and Brooks between I/O channels and I/O
  processors, which is the general ability to count.  That is, an I/O processor
  should have the ability to maintain a loop or event count that is unrelated
  to the transfer of a given number of words or characters per block.

From this definition, I credit the IBM 709 with the first "channel".

  IBM 709 (1957) - introduction of channel I/O [5,6,32].  The CPU must execute
  two instructions in sequence to start I/O.  A read select or write select
  instruction is first used to select a given device, and then a channel-
  specific instruction is used to reset and start any of the maximum of six
  channels (766s).  The address field of the reset and start instruction is
  used to carry the channel program address.  Some device select instructions
  are interlocked so that the CPU is stalled if a second select is issued
  before a previous one ends.  The reset and select instructions, however,
  immediately act upon the channels, which were much more sophisticated than
  the later IBM S/360 channels.  Polling can be used for I/O completion, while
  interruption ("data-channel trap") is available as an extra cost feature.
  Apparently, all installations chose to use the interrupt feature [M.
  Rubinstein, personal communication].

  IBM 7090 (1958) [8,10].  The optional "data-channel trap" feature of the
  709 architecture is included as standard equipment.  An interrupt vector
  with a pair of saved-PC and new-PC locations for each channel is used to
  resolve I/O completion traps.  The later version channels (7909) can
  themselves be interrupted by external events and are capable of dealing
  with I/O retries without CPU intervention.

I would appreciate learning of other historical machines that were not
included in my CAN article.

-- 
Mark Smotherman, CS Dept., Clemson University, Clemson, SC 29634-1906
  (803) 656-5878,  [email-masked]  or  [email-masked]